1. Field of the Invention
This invention generally relates to semiconductor devices or structures and fabrication methods therefor and more particularly relates to improved planar type silicon semiconductor devices or structures including fabrication processes therefor having recessed oxide regions located in the silicon.
2. Description of the Prior Art
In the past, the semiconductor device technology has developed from the fabrication of only discrete devices to the present process of making complex integrated circuits containing thousands of individual devices. In the early days of the semiconductor industry when all the devices being made were discrete devices, these discrete devices were made with semiconductor regions of either N or P type conductivity which were located in various portions of the semiconductor substrate.
Many process and resulting structural changes were developed including a process generally known in the semiconductor industry as the "planar process". In the planar process, all the semiconductor regions of either P or N type conductivity were formed or located in one planar (i.e. top) surface portion of the semiconductor (silicon) substrate rather than in various surface portions of the semiconductor substrate.
The planar process technology is utilized to a great extent in making integrated circuits. In the planar process technology all diffusions or ion implantations of P or N type conductivity are carried out using one surface of the semiconductor structure or substrate.
In one example, the starting semiconductor substrate or structure made of, for example, silicon, will generally receive at least one protective or insulating surface coating of, for example, silicon dioxide. In some other examples, two or more protective or insulating layers or surface coatings are formed using, for example, silicon dioxide and silicon nitride layers. In the use of a combined silicon dioxide-silicon nitride protective or insulating layered combination, the underlying oxide layer (in contact with the silicon surface) serves to remove surface stresses from active areas on the silicon surface which would occur if the silicon nitride layer was formed directly on the silicon surface without the underlying intermediate silicon dioxide layer.
The oxide layer may be thermally grown by exposing the silicon surface to an oxidizing atmosphere at elevated temperatures. Alternately, the oxide may be deposited by pyrolytic deposition or RF sputtering techniques. The silicon nitride, Si.sub.3 N.sub.4, may be formed on the oxide surface by exposing it to an atmosphere of silane and ammonia in an RF reactor. Other silicon nitride deposition techniques may be utilized, as desired.
When it is desired to provide an active area in the silicon surface, a photoresist coating is applied to the entire top surface of the semiconductor, over the nitride layer. When exposed to ultraviolet light through a mask which defines a desired pattern and developed, there will remain areas of the nitride surface which are unprotected by the developed photoresist coating. These unprotected areas are susceptable to being etched away. When the slice is subjected to a plasma etch, the exposed nitride areas will be removed down to the oxide layer. The exposed oxide layer may be removed using a buffered HF solution. Diffusion processes or epitaxial growth techniques may now be employed to alter the characteristics of the patterned areas exposed by removal of the nitride and oxide layers. Alternatively, ion implantation can be used to form P or N type regions in the exposed semiconductor substrate.
Planar technology consists of a multiplicity of such steps as just described; each operation creating an active surface area in the semiconductor substrate following removal of remaining oxide and nitride layers. These layers are photomasked and photoetched to expose the surfaces of the semiconductor material to which diffusion and epitaxial growth techniques may be applied as required to generate an integrated circuit on the semiconductor wafer or substrate.
It frequently is required to provide a thick oxide layer in a selected portion or surface of the semiconductor. This thick oxide layer is to remain in place within said semiconductor surface so as to isolate it from other active surfaces of the semiconductor. This thick oxide layer is created by, for example, exposing patterned areas of the semiconductor wafer to oxidizing conditions. The thick oxide layer will be grown only on the exposed silicon surface since the top nitride layer remaining after the photoetching process will act as a mask to prevent thereon oxidization build up. Since the thick oxide layer used for side wall isolation is grown in the patterned recesses defined by the etching away of the nitride and oxide layers, it was expected that the thick oxide layer would have a width no greater than that of the width of the recess, which, in itself, is determined by the earlier masking and photoetching processes. In point of fact however, it was found that the thick oxide layer grown within these recesses extends sideways beyond the limits defined by the recess. This caused the thick oxide layer to extend into the active region of the semiconductor adjacent to which it was placed for isolation purposes. As a result of this extension beyond the patterned region of the semiconductor surface defined by the etched recess, there remained less of the semiconductor surface available for subsequent use. Thus, utilization of the semiconductor surface was reduced and valuable semiconductor real estate was lost.
The growth extension regions of the thick oxide layer take on a characteristic shape which has been denoted in the art as a "birdbeak". Because these "birdbeak" extensions usurp valuable area on the semiconductor surface, these extensions place undesirable limitations on the effectiveness of very large scale integration (VLSI) procedures.
Accordingly, a need existed to provide an improved semiconductor device or structure or fabrication method therefor which would eliminate the formation of "birdbeak" recessed oxide isolation (ROX) regions.